1. Field of the Invention
This invention relates to a high-speed random-cycle external-clock synchronous semiconductor memory device with a plurality of memory banks. More particularly, this invention relates to an improvement in a bank timer circuit that determines a restore period and a precharge starting time in a random cycle time.
2. Description of the Related Art
With recent advances in information technology, there is an increasing demand for semiconductor memories. At the same time, semiconductor memory devices are required to operate faster. Under such conditions, more and more synchronous DRAMs (SDRAMs) that operate in synchronization with an external clock signal have been used instead of memory devices not synchronizing with an external clock signal, such as EDO memories.
There are two types of SDRAMs: single data rate SDRAMs (SDR SDRAMs) and double data rate SDRAMs (DDR SDRAMs). The SDR SDRAM outputs data in synchronization with only the rising edge of the clock signal. The DDR SDRAM outputs the data in synchronization with both the rising edge and the falling edge of the clock signal. Therefore, the DDR SDRAM has a data transfer rate twice as high as that of the SDR SDRAM.
To make the data rate of the DDR SDRAM higher, it is necessary to make the random cycle time (tRC) in the memory core section shorter. The DRAM does destructive reading of cell data. Therefore, when the memory cell selected at a certain address accesses the memory cell corresponding to another row address (or a different word line), a restore operation and a precharge operation are needed, which makes it difficult to makes the random cycle time shorter.
To overcome this drawback, a fast cycle RAM has been developed which has a remarkably improved random access time resulting from improving the core architecture and carrying out an internal operation in a pipelined manner. In the fast cycle RAM, the operation modes, including data write, data read, and refresh, are set by a combination of a first command and a second command.
As described above, the DRAM does destructive reading of cell data. For this reason, a series of operations to access memory cells requires the restore time (tRAS) for selecting a word line, setting the word line at a high potential, and writing the data into the memory cells again and the precharge time (tRP) for precharging a bit line pair, regardless of whether the data is read or written. Therefore, only when the time (tRAS+tRP) has elapsed since a certain address was accessed, the next address cannot be accessed; otherwise the word line is selected doubly. The reason is that all the memory cells are controlled in common.
To overcome the disadvantage, the memory device is divided into a plurality of banks and each bank is controlled independently. With the memory device composed of a plurality of banks, even when memory cells in a certain bank are being accessed, it is possible to access memory cells in a different bank immediately.
Here, the operation in reading the data in a fast cycle RAM with a plurality of banks will be explained. At the same time that a first command corresponding to the data read operation is input, a bank address for determining which bank to access is input. Therefore, after the first command is accepted, the bank corresponding to the input bank address is selected. The length of the period during which the bank is kept selected is equivalent to the length of the period during which the word line is kept driven. The bank select signal for selecting the bank is controlled so as to make the bank unselected automatically after a certain time has elapsed. This control is performed by a bank timer circuit. The bank timer circuit determines the length of the restore time and the starting time of a precharge operation after the restore time.
A conventional bank timer circuit includes an RC delay circuit composed of a resistance element and a capacitance element. In the RC delay circuit, a delay time determined by an RC time constant is set. Then, the delay time determines the length of the restore time and the starting time of the precharge operation.
The resistance element used in the RC delay circuit is highly dependent on processes. That is, the resistance element varies greatly, depending on manufacturing processes. Furthermore, it also varies greatly, depending on external factors, such as temperature and voltage. Therefore, in the conventional bank timer circuit, the length of the restore time and the starting time of the precharge operation vary. As a result, for example, when the length of the restore time gets shorter than the determined length, the restore time cannot be secured sufficiently, leading to a decrease in the amount of data written and therefore causing insufficient restoration, which makes it impossible to secure a sense margin for the next cycle. Therefore, the bank timer circuit is required to have no dependence on processes and always make the length of the restore time and the starting time of the precharge operation stable.